tristate logic (TSL)

In the transistor-transistor logic circuits, the circuit added with an inhibiting input. If the inhibiting input is low level, the circuit has two states, i.e. , high level and low level; If inhibiting input is high level, the circuit appears the third state, i.e., the output terminal is the open state.; 在晶體管-晶體管邏輯電路中加上禁止輸入的電路。在禁止輸入為低電平時，電路有兩種狀 態，即高電平和低電平；當禁止輸入為高電平時，電路呈現第三種狀態，即輸出端為開路狀態。